1. Field of the Invention
The invention relates to storage subsystems and in particular to improved performance in a storage subsystem that includes networked hierarchical components within the storage subsystem where transactions within the system may incur latencies.
2. Related Patents
This patent application is related to co-pending, commonly owned U.S. patent application Ser. No. 02-5574, entitled METHOD AND APPARATUS FOR HANDLING STORAGE REQUESTS, filed the same day which is hereby incorporated by reference and is referred to herein as the “related patent.”
3. Discussion of Related Art
Computing systems and applications use persistent storage devices and subsystems to store and retrieve information. Storage subsystem requirements for capacity, performance and reliability continue to grow as corresponding needs grow in such storage subsystem applications.
It is generally known in the art to use redundant arrays of independent/inexpensive disks (typically referred to by the acronym RAID) to improve both performance and reliability of storage subsystems. RAID storage management techniques, in general, distribute stored information over a plurality of disk drives. Such distribution of stored information over a plurality of disk drives improves performance by distributing associated seek and rotational latencies over multiple disk drives operating in parallel. In general, additional disk drives degrade overall subsystem reliability by increasing the number of potentially failing components and hence reducing mean time between failure of the associated system. RAID techniques enhance reliability by generating redundancy information associated with all stored information and storing such redundancy information along with host supplied data. The redundancy information, in general, allows a RAID storage subsystem to survive failure of a single disk drive in the array and permits continued operation though potentially in a degraded mode.
In some storage system architectures, it is known to utilize an I/O module (“IOM”) associated with the storage system to serve as an interface between attached host systems and lower-level storage elements sometimes referred to as storage building blocks (“SBB”). Examples of such system architectures are described in the related patent.
In such an architecture it is common that the I/O module and storage building blocks are interconnected through one or more communication structures including, for example, a PCI bus (in particular, a PCI-X bus is a common architecture often utilized in such embedded applications). Regardless of the particular communication medium used to interconnect the I/O module and storage building block, it is common in that some latency will be imposed between the read request (directed from the I/O module to the associated storage building block) and the corresponding return of requested data from the storage building block to the I/O module (for ultimate return to the requesting host system).
In such an architecture it is common that the I/O module and storage building blocks are interconnected through one or more communication structures including, for example, a PCI bus (in particular, a PCI-X bus is a common architecture often utilized in such embedded applications). Regardless of the particular communication medium used to interconnect the I/O module and storage building block, it is common in that some latency will be imposed between the read request (directed from the I/O module to the associated storage building block) and the corresponding return of requested data from the storage building block to the I/O module (for ultimate returned to the requesting host system).
More specifically in one exemplary embodiment described in the above referenced co-pending patent applications, a PCI-X bus is utilized in a portion of the path communicating between an I/O module and the storage building block. More specifically, a PCI-X bus is used within the IOM to couple a front-end host communication channel interface (such as Fibre Channel) to a back-end SBB interface (such as a custom ASIC for switched fabric communication). In such an exemplary embodiment, the I/O module front-end issues a PCI-X read request directed toward the IOM back-end interface to the appropriate storage building block. The IOM front-end receives a split transaction from the storage building block indicating that a delay may be incurred as the storage building block retrieves and/or otherwise prepares the requested data. Eventually, the storage building block returns the requested data and completes the entire transaction with a split transaction completion indication on the PCI-X bus.
Such a transaction will incur a latency as the storage building block performs overhead processing associated with identifying and retrieving the requested block of information (even when the requested block already resides in higher speed cache memory within the storage building block).
In high-performance storage applications, such latency delays impose undesirable limitations on storage subsystem bandwidth especially for high-performance read requirements in storage subsystem applications. It is evident from the above discussion that an ongoing problem exists to improve available bandwidth utilization in storage subsystems utilizing internal bus structures for communication between I/O control elements and storage elements and to thereby improve overall storage subsystem performance.